Electronic circuit simulators are often used by integrated circuit designers to optimize the design of an integrated circuit (IC). A circuit simulator typically handles the IC in a node/element fashion such that the circuit is regarded as a collection of circuit elements, which are connected at nodes. Common circuit elements include resistors, capacitors, inductors, mutual inductors, diodes, transistors, and interconnect lines, etc. To simulate the IC, each circuit element needs to be properly modeled.
Traditional circuit simulators have ignored parasitic inductance when modeling some of the circuit elements such as interconnect lines in the ICs. The operating frequencies of these ICs were low enough so that induced voltages were generally negligible compared to the effects of parasitic resistance and capacitance in the ICs. With increasing clock speeds and decreasing feature sizes of very large scale integrated circuits (VLSI), interconnect issues, especially variation in signal delays and skews due to parasitic inductance, now play a vital role in the performance of VLSI circuits. In fact, parasitic elements in the interconnects are becoming limiting factors in determining circuit performance. Thus, accurate analysis and careful design of interconnects are of critical importance in realizing quality designs of VLSI circuits, and parasitic inductance is an important factor to be considered when analyzing and designing the interconnects of the VLSI circuits.
To analyze the effects of parasitic resistance (R), capacitance (C), and inductance (L) associated with the interconnects of an IC, the R, C, and L need to be extracted at chip level. Several techniques have been developed to extract the R and C on chip. An example of these techniques has been discussed by Chen, et al. in “An On-Chip, Attofarad Interconnect Charge-based Capacitance Measurement (CBCM) Technique,” IEDM 96, 3.4.1. The techniques for on-chip parasitic inductance extraction, however, are less developed. At the moment, there is no commercial tool available for on-chip parasitic inductance measurement. The difficulty of directly measuring the parasitic inductance of interconnect lines arises from the associated small inductance values, the requirement of high frequency instruments, and the difficulty in excluding the capacitance and inductance of contact pads, wires, and probes, etc., which are necessary for connecting the interconnect lines to the high frequency instruments.